1. Field of the Invention
The present invention relates to, for example, a MOS-type semiconductor device, and more specifically, to a semiconductor device having gate oxide films having two or more different thicknesses on the same substrate and the manufacturing method therefor.
2. Description of the Related Art
There is a great demand for MOS-type semiconductor devices because of their high densities, their high reliabilities and their high performances. Some of the MOS-type semiconductor devices use a plurality of power sources. For example, a non-volatile memory uses a high voltage of about 12V for writing and erasing data unlike for a general reading of data. Consequently, the element which constitutes a circuit for writing or erasing data should be of a high voltage-withstanding type which can withstand a high voltage. Further, a voltage of about 5V is used for a general reading of data. Therefore, the element which constitutes the reading circuit need not be a high voltage withstanding type, but the element may be of a low voltage withstanding type. Thus, a non-volatile memory has a structure in which high voltage withstanding elements and low voltage withstanding elements are mixedly provided in a single semiconductor device.
Due to the presence of the high voltage withstanding elements, there is a tendency for the thickness of the gate oxide film to increase. This is because the reliability of the gate oxide film can be maintained high by increasing the thickness of the gate oxide film so as to relax an electrical field applied to the gate oxide film. However, if the thickness of the gate oxide film is increased, the driving performance of the elements is decreased. In other words, the driving performance of the low voltage withstanding elements, which need not withstand a high voltage, is also decreased, thus creating a problem with regard to the demand for a high density and a high level of performance of the semiconductor device. In order to remove this problem, generally, a thin gate oxide film should be used for a low voltage withstanding element to which a low voltage is supplied, and a thick gate oxide film should be used only for a high voltage withstanding element to which a high voltage is conventionally supplied, so that the above adverse influence is not propagated to the low voltage withstanding elements formed within the same substrate. For this reason, an element having two types of gate oxide films within a semiconductor device, is used.
FIGS. 5A to 8B each illustrate a manufacturing step of forming an N-type transistor having two types of gate oxide films. First, as shown in FIG. 5A, an element separation oxide film (to be called as element separation region hereinafter) 32 is formed in a surface region of a P-type semiconductor substrate 31 by a known LOCOS (selective oxidization) method. Then, dummy oxide films 33a and 33b are formed on the surface of the semiconductor substrate 31.
Next, as shown in FIG. 5B, a resist pattern 34 is formed on the dummy oxide film 33a and the element separation region 32. With use of the resist pattern 34 as a mask, a P-type impurity used for controlling the threshold voltage, namely, boron, is doped into a first region HV, which is supposed to be formed into an element to which a high voltage, for example, 12V, is applied.
After the resist pattern 34 is removed, a resist pattern 35 is formed on the dummy oxide film 33b and the element separation region 32 as shown in FIG. 5C. With use of the resist pattern 35 as a mask, a different amount of P-type impurity, from that used for the first region HV is doped into a second region LV, which is supposed to be formed into an element to which a low voltage is applied. With this structure, a predetermined threshold voltage can be set even in the case where the thickness of the gate oxide film to be formed in the first region HV differs from that of the gate oxide film to be formed in the second region LV.
Next, as shown in FIG. 6A, after the resist pattern 35 is removed, a resist pattern 36 which corresponds to the second region LV is formed. With use of the resist pattern 36 as a mask, the dummy oxide film 33b of the first region HV is removed by etching as shown in FIG. 6B. Further, after the resist pattern 36 is removed, a thick gate oxide film 37 is formed on the portion of the semiconductor substrate 31, which corresponds to the position of the first region HV, as shown in FIG. 6C.
As shown in FIG. 7A, a resist pattern 38 is formed on the first region HV. With use of this pattern as a mask, the dummy oxide film 33a on the second region LV is removed by etching as shown in FIG. 7B. Further, after the resist pattern 38 is removed, a thin gate oxide film 39 is formed on the portion of the semiconductor substrate 31, which corresponds to the position of the second region LV as shown in FIG. 7C.
After the gate oxide films 37 and 39 having different thicknesses are formed as described above, a high voltage withstanding element and a low voltage withstanding element are formed in the first region HV and the second region LV, respectively, by a conventional method of manufacturing a MOS transistor.
The two resist patterns 36 and 38 used for removing the dummy oxide films 33b and 33a, while forming the gate oxide films 37 and 39 having different thicknesses, are formed so that edge portions of these patterns meet with each other at the central portion of the surface of the element separation region 32. However, on the element separation region 32, the position of the mask used to form the resist pattern 36 is in some cases displaced from the position of the mask for the resist pattern 38. In such a case, a recess portion 40, for example, is formed on the element separation region 32 as shown in FIG. 8A, or a projection portion 41, for example, is formed on the element separation region 32 as shown in FIG. 8B. In the case shown in FIG. 8A, where the recess portion 40 is formed on the element separation region 32, a resist material or a gate electrode material, which is likely to serve as a source of generating dust, enters in the recess portion 40 in a later step, which lowers the yield of the products and therefore adversely affects the reliability of the products.
Further, as shown in FIG. 8B, for example, if the projection portion 41 is formed on the element separation region 32, the projection portion 41 serves as a source of generating dust. In the case where the recess portion 40 or the projection portion 41 is formed, conventionally, such an irregularity is removed by the etching process including the photolithography step, thus increasing the number of steps.
Further, in the case where the resist patterns 36 and 38 are formed, the entire surface of the element separation region 32 is etched in both steps of etching the dummy oxide film 33a. Consequently, the element separation region 32 is thinned, and the inverse withstand of the parasitic field transistor which regards the element separation region 32 as a gate insulation film, is lowered, thus deteriorating the element separating effect. Therefore, in order to assure the element separation, the width of the element separation region must be widened, which creates a problem of blocking the downsizing of the semiconductor device.